This article proposes a VHDL language course that establishes a strong correlation between the language statements and their use in circuit synthesis. Two course modules are described: a basic module that contains the essential concepts of the language, sufficient for students to describe medium complexity circuits, followed by a second module with more complex language concepts. The benefits of correlated laboratory tasks which use simulation and synthesis tools are discussed. Evaluation content, student test scores, and student feedback are presented. Suggestions for improving and modifying the course are given.