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ERIC Number: EJ900581
Record Type: Journal
Publication Date: 2010-May
Pages: 10
Abstractor: As Provided
Reference Count: 21
ISSN: ISSN-0018-9359
System-on-Chip Design and Implementation
Brackenbury, L. E. M.; Plana, L. A.; Pepper, J.
IEEE Transactions on Education, v53 n2 p272-281 May 2010
The system-on-chip module described here builds on a grounding in digital hardware and system architecture. It is thus appropriate for third-year undergraduate computer science and computer engineering students, for post-graduate students, and as a training opportunity for post-graduate research students. The course incorporates significant practical work to illustrate the material taught and is centered around a single design example of a drawing machine. The exercises are composed so that students can regard themselves as part of a design team where they undertake the complete design of their own particular section of the system. These design tasks range from algorithmic specification and transaction-level modeling (TLM) of the architecture down to describing the design at the register transfer level (RTL) with subsequent verification of their prototype on a field-programmable gate array (FPGA). With this approach, students are able to explore and gain experience of the different techniques used at each level of the design hierarchy and the problems in translating to the next level down. Throughout the module, there is emphasis on using industry standard tools for the modeling and simulation, leading to the use of the SystemC and Verilog hardware description languages and Cadence for the simulation environment. (Contains 8 figures and 2 tables.)
Institute of Electrical and Electronics Engineers, Inc. 445 Hoes Lane, Piscataway, NJ 08854. Tel: 732-981-0060; Web site:
Publication Type: Journal Articles; Reports - Descriptive
Education Level: Higher Education
Audience: Teachers
Language: English
Sponsor: N/A
Authoring Institution: N/A
Identifiers - Location: United Kingdom